`include "timescale.v"

module onu_mac_ctrl(
	input  	   	   Rx_clk					,
	input  	   	   Rx_dv					,
	input	   	   Rx_er					,
	input  [7:0]   Rxd						,
	
	input	   	   Col						,	
	input	   	   Crs						,
	
	// output 		   Gtx_clk					,//used only in GMII mode
	input 		   Gtx_clk,						//this signal should supplied by the Reconciliation Sublayer !
	output 		   Tx_en					,
	output 		   Tx_er					,
	output [7:0]   Txd						,
	
	input		   reset,						//this should connect to the IP core reset signal ???

	//for tx fifo inteface (fifo's clk is Gtx_clk)
	input  [7:0]   tx_fifo_data,
	input 		   tx_fifo_empty,
	input 		   tx_fifo_rd_en
	);

wire 			  mpcp_pause_addr_ok, oam_addr_ok;
onu_rx onu_rx1(
	.reset					(reset),
	.Rx_clk					(Rx_clk),
	.Rx_dv					(Rx_dv),
	.Rx_er					(Rx_er),
	.Rxd					(Rxd),

	.MAC					(48'h4012_3456_789A),
	.transmitting			(1'b0),

	.MPCP_PAUSE_Addr_OK		(mpcp_pause_addr_ok),
	.OAM_Addr_OK			(oam_addr_ok)
	);


reg 			  TxStartFrm, TxEndFrm;
onu_tx onu_tx1(
	.reset					(reset),
	
	.Tx_clk					(Gtx_clk),			//GMII interface 
	.Tx_en					(Tx_en),
	.Tx_er					(Tx_er),
	.Txd					(Txd),

	.MinFL					(16'h40),
	.MaxFL					(16'h600),
	.IPGT					(4'd12),

	.TxStartFrm				(TxStartFrm),
	.TxEndFrm				(TxEndFrm),

	.TxUnderRun				(1'b0),
	
	//output 
	.StatePreamble			(),
	.StateData				()
	);


initial begin
  TxStartFrm = 1'b0; 
  TxEndFrm = 1'b0; 
  #200 TxStartFrm = 1;
  #9 TxStartFrm = 0;
  #500 TxEndFrm = 1;
  #9 TxEndFrm = 0;
end

endmodule